Information is written to memory cells, in particular MRAM memory cells, by electric currents which flow from a constant-current source with respect to a fixed potential, such as, in particular, ground. Depending on their direction, these currents bring about a parallel or antiparallel orientation of the polarization of magnetoresistive layers that are separated by a tunnelling barrier layer within an individual memory cell of the MRAM array. As is known, a parallel orientation of the polarization is assigned a lower resistance than an antiparallel orientation of the polarization. Pulses are used for write currents, the pulse amplitude rather than the pulse duration being critical for the write operation.
During a write operation to a selected memory cell at the crossover between a specific word line and a specific bit line, in addition to magnetic energy, electrical energy is also converted into thermal energy, and thus consumed, as a result of the voltage drop across the line resistances of the word line or bit line. Overall, the energy balance (or “efficiency”) is extremely unfavourable since a large part of the electrical energy is transformed into heat.
In addition to this energy loss, measures have to be taken so that the voltage drop across individual memory cells of memory cell arrays of varying sizes is kept uniform.
Moreover, when reading from a memory cell, a current pulse specifying the stored information flows, wherein the current pulse has a larger amplitude in the case of a lower resistance (parallel orientation of the polarization) than in the case of a higher resistance (antiparallel orientation of the polarization) and can thus represent a cell content as “1” or “0”. In a similar manner to a write current, such a current pulse brings about an energy loss in the form of heat.
Hereinafter, the writing to and reading from a memory cell in a memory cell array of the memory arrangement will also be referred to as “addressing” or “setting”.
As described below previous attempts at addressing this energy loss problem have not yielded promising results.
As is known, the interconnect resistance of a word line, bit line, or additional write line is determined by the specific conductivity of the interconnect material, the interconnect cross-sectional area and length. To avoid excessively large voltage drops across memory cells in a memory arrangement (also hereinafter referred to as a “memory circuit”) and thus to reduce the risk of electrical breakdowns, the interconnects are designed with the least possible resistance, and the residual voltage remaining after setting is “consumed” in resistors connected downstream. In other words, losses in the interconnects and, in particular, in the resistors connected downstream are thus deliberately accepted. This means, however, that the energy balance is highly unfavourable in the case of such existing memory arrangements.